Self-timed circuit techniques have long been used in memory designs, finding their way into both static and dynamic random access memories (RAMs) and the more complex content addressable memories (CAMs). Testing memories with these designs, however, can be very difficult as self-timed circuitry tends to provide little insight into internal operation, making observability at the input and output pins only.
In RAMs, the function being performed is simple enough that testability can be secondary priority in the overall design process. That is, the sole function of a simple RAM is to store and retrieve data, and this can be performed with self-timed techniques rather easily. Failures can, thus, be determined readily as the function is not extremely complex.
In CAM architectures, such as those being utilized as caches, the problem is not so simple. In such architectures, arrays of tag bits are compared with an incoming address to check for a match. If such a match occurs, then a secondary memory is accessed to select the desired information. If a match is not found, the information is typically retrieved from the main memory and sent to the requestor as well as being stored in the CAM.
Problems, then, arise in the access of the secondary memory. Since the tag matching function may select any memory location in the secondary memory array, it is typically extremely difficult to determine which location has been selected. This creates a problem in determining which locations in the secondary memory (if any) are failing due to process errors, design problems, etc. Determining which memory location has failed is extremely important as factors in manufacturing, such as in bitmapping the memory array for fault isolation to direct design characterization, design modifications, and repairing with redundant elements.
There are typically two basic types of CAM architecture being utilized as a cache: clocked cache architecture and self-timed cache architecture.
Typically, in a clocked cache architecture, determination of which locations in the secondary memory can be accomplished by channeling signals utilized to select a location in the secondary memory through a set of latches. The set of latches are typically set up to receive and forward the selection signals in a serial fashion to the secondary memory.
In self-timed caches, an operational clock is not available for resetting the set of latches. Therefore, the conventional configuration of CAM, secondary memory and latches is not suitable for a self-timed cache.
Accordingly, what is needed is a method and system for determining which secondary memory array location has been accessed in a self-timed cache. The present invention addresses such a need.